chipsalliance · SpriteOvO · Aug 30, 2024 · Sep 3, 2024 · Sep 3, 2024
diff --git a/.github/workflows/test.yml b/.github/workflows/test.yml
@@ -82,6 +82,69 @@ jobs:
         #      support binary compatibility for the plugin
         run: sbt ++${{ inputs.scala }} unipublish/mimaReportBinaryIssues
 
+  repro-scala-cli-bug:
+    name: repro-scala-cli-bug
+    runs-on: ubuntu-22.04
+    steps:
+      - name: Checkout
+        uses: actions/checkout@v4
+        with:
+          ref: ${{ inputs.ref }}
+      - name: Setup Java
+        uses: actions/setup-java@v4
+        with:
+          distribution: 'adopt'
+          java-version: '21'
+      - name: Pick CIRCT version
+        id: circt-version
+        run: |
+          if [[ -z "${{ inputs.circt }}" ]]; then
+            echo "version=version-file" >> "$GITHUB_OUTPUT"
+          else
+            echo "version=${{ inputs.circt }}" >> "$GITHUB_OUTPUT"
+          fi
+      - name: Install CIRCT
+        uses: circt/[email protected]
+        with:
+          version: ${{ steps.circt-version.outputs.version }}
+          github-token: ${{ github.token }}
+      - name: Setup Scala-cli
+        run: |
+          curl -fL https://github.com/Virtuslab/scala-cli/releases/latest/download/scala-cli-x86_64-pc-linux.gz | gzip -d > scala-cli
+          chmod +x scala-cli
+          sudo mv scala-cli /usr/local/bin/scala-cli
+      - name: Run Tests
+        run: |
+          echo 'println("hello world")' > ./scala-cli-test.sc
+          ./mill version &
+          scala-cli --server=false ./scala-cli-test.sc
+          scala-cli --server=false ./scala-cli-test.sc
+          scala-cli --server=false ./scala-cli-test.sc
+          scala-cli --server=false ./scala-cli-test.sc
+          scala-cli --server=false ./scala-cli-test.sc
+          scala-cli --server=false ./scala-cli-test.sc
+          scala-cli --server=false ./scala-cli-test.sc
+          scala-cli --server=false ./scala-cli-test.sc
+          scala-cli --server=false ./scala-cli-test.sc
+          scala-cli --server=false ./scala-cli-test.sc
+          scala-cli --server=false ./scala-cli-test.sc
+          scala-cli --server=false ./scala-cli-test.sc
+          scala-cli --server=false ./scala-cli-test.sc
+          scala-cli --server=false ./scala-cli-test.sc
+          scala-cli --server=false ./scala-cli-test.sc
+          scala-cli --server=false ./scala-cli-test.sc
+          scala-cli --server=false ./scala-cli-test.sc
+          scala-cli --server=false ./scala-cli-test.sc
+          scala-cli --server=false ./scala-cli-test.sc
+          scala-cli --server=false ./scala-cli-test.sc
+          scala-cli --server=false ./scala-cli-test.sc
+          scala-cli --server=false ./scala-cli-test.sc
+          scala-cli --server=false ./scala-cli-test.sc
+          scala-cli --server=false ./scala-cli-test.sc
+          scala-cli --server=false ./scala-cli-test.sc
+          scala-cli --server=false ./scala-cli-test.sc
+          scala-cli --server=false ./scala-cli-test.sc
+          scala-cli --server=false ./scala-cli-test.sc
   mill:
     name: compile project with mill
     runs-on: ubuntu-22.04
@@ -112,10 +175,33 @@ jobs:
         with:
           version: ${{ steps.circt-version.outputs.version }}
           github-token: ${{ github.token }}
+      - name: Set CIRCT Path Env
+        run: echo "CIRCT_INSTALL_PATH=$(pwd)/circt" >> $GITHUB_ENV
+      - name: Watch the file
+        run: |
+          sudo apt install auditd
+          sudo systemctl start auditd
+          sudo auditctl -w /home/runner/.cache/scalacli/local-repo/.1.5.0.tmp/version -p war
+      - name: Install Lit
+        run: pip install lit
       - name: Compile Mill
+        run: ./mill --no-server __.compile
+      - name: Setup Scala-cli
+        run: |
+          curl -fL https://github.com/Virtuslab/scala-cli/releases/latest/download/scala-cli-x86_64-pc-linux.gz | gzip -d > scala-cli
+          chmod +x scala-cli
+          sudo mv scala-cli /usr/local/bin/scala-cli
+      - name: Run Lit Tests
+        run: ./mill --no-server lit[${{ inputs.scala }}].run
+      - name: Debug
+        if: always()
         run: |
-          export CIRCT_INSTALL_PATH="$(pwd)/circt"
-          ./mill __.compile
+          scala-cli --version
+          tree /home/runner/.cache/scalacli/local-repo
+          echo "======="
+          cat /home/runner/work/chisel/chisel/out/lit/2.13.14/litConfig.dest/Converter/.scala-build/stacktraces/*
+          echo "======="
+          sudo ausearch -f /home/runner/.cache/scalacli/local-repo/.1.5.0.tmp/version
 
   doc:
     name: Formatting

diff --git a/lit/tests/Converter/Module.sc b/lit/tests/Converter/Module.sc
@@ -1,4 +1,4 @@
-// RUN: scala-cli --server=false --java-home=%JAVAHOME --extra-jars=%RUNCLASSPATH --scala-version=%SCALAVERSION --scala-option="-Xplugin:%SCALAPLUGINJARS" --java-opt="--enable-native-access=ALL-UNNAMED" --java-opt="--enable-preview" --java-opt="-Djava.library.path=%JAVALIBRARYPATH" %s | FileCheck %s -check-prefix=FIRRTL
+// RUN: scala-cli --server=false --java-home=%JAVAHOME --extra-jars=%RUNCLASSPATH --scala-version=%SCALAVERSION --scala-option="-Xplugin:%SCALAPLUGINJARS" --java-opt="--enable-native-access=ALL-UNNAMED" --java-opt="--enable-preview" --java-opt="-Djava.library.path=%JAVALIBRARYPATH" %s | FileCheck %s -check-prefix=FIRRTL -check-prefix=VERILOG
 // SPDX-License-Identifier: Apache-2.0
 
 import chisel3._
@@ -96,91 +96,25 @@ class Mem extends Module {
 
 println(lit.utility.panamaconverter.firrtlString(new Mem))
 
-// FIRRTL-LABEL: public module Sram :
-// FIRRTL-NEXT:   input clock : Clock
-// FIRRTL-NEXT:   input reset : UInt<1>
 class Sram extends Module {
-  // FIRRTL:      wire mem
-  // FIRRTL:      mem mem_sram
-  // FIRRTL:      connect mem_sram.R0.addr, mem.readPorts[0].address
-  // FIRRTL-NEXT: connect mem_sram.R0.clk, clock
-  // FIRRTL-NEXT: connect mem.readPorts[0].data, mem_sram.R0.data
-  // FIRRTL-NEXT: connect mem_sram.R0.en, mem.readPorts[0].enable
-  // FIRRTL-NEXT: connect mem_sram.R1.addr, mem.readPorts[1].address
-  // FIRRTL-NEXT: connect mem_sram.R1.clk, clock
-  // FIRRTL-NEXT: connect mem.readPorts[1].data, mem_sram.R1.data
-  // FIRRTL-NEXT: connect mem_sram.R1.en, mem.readPorts[1].enable
-  // FIRRTL-NEXT: connect mem_sram.W0.addr, mem.writePorts[0].address
-  // FIRRTL-NEXT: connect mem_sram.W0.clk, clock
-  // FIRRTL-NEXT: connect mem_sram.W0.data, mem.writePorts[0].data
-  // FIRRTL-NEXT: connect mem_sram.W0.en, mem.writePorts[0].enable
-  // FIRRTL-NEXT: connect mem_sram.W0.mask, UInt<1>(1)
-  // FIRRTL-NEXT: connect mem_sram.W1.addr, mem.writePorts[1].address
-  // FIRRTL-NEXT: connect mem_sram.W1.clk, clock
-  // FIRRTL-NEXT: connect mem_sram.W1.data, mem.writePorts[1].data
-  // FIRRTL-NEXT: connect mem_sram.W1.en, mem.writePorts[1].enable
-  // FIRRTL-NEXT: connect mem_sram.W1.mask, UInt<1>(1)
-  // FIRRTL-NEXT: connect mem_sram.RW0.addr, mem.readwritePorts[0].address
-  // FIRRTL-NEXT: connect mem_sram.RW0.clk, clock
-  // FIRRTL-NEXT: connect mem_sram.RW0.en, mem.readwritePorts[0].enable
-  // FIRRTL-NEXT: connect mem.readwritePorts[0].readData, mem_sram.RW0.rdata
-  // FIRRTL-NEXT: connect mem_sram.RW0.wdata, mem.readwritePorts[0].writeData
-  // FIRRTL-NEXT: connect mem_sram.RW0.wmode, mem.readwritePorts[0].isWrite
-  // FIRRTL-NEXT: connect mem_sram.RW0.wmask, UInt<1>(1)
-  // FIRRTL-NEXT: connect mem_sram.RW1.addr, mem.readwritePorts[1].address
-  // FIRRTL-NEXT: connect mem_sram.RW1.clk, clock
-  // FIRRTL-NEXT: connect mem_sram.RW1.en, mem.readwritePorts[1].enable
-  // FIRRTL-NEXT: connect mem.readwritePorts[1].readData, mem_sram.RW1.rdata
-  // FIRRTL-NEXT: connect mem_sram.RW1.wdata, mem.readwritePorts[1].writeData
-  // FIRRTL-NEXT: connect mem_sram.RW1.wmode, mem.readwritePorts[1].isWrite
-  // FIRRTL-NEXT: connect mem_sram.RW1.wmask, UInt<1>(1)
-  // FIRRTL-NEXT: connect mem_sram.RW2.addr, mem.readwritePorts[2].address
-  // FIRRTL-NEXT: connect mem_sram.RW2.clk, clock
-  // FIRRTL-NEXT: connect mem_sram.RW2.en, mem.readwritePorts[2].enable
-  // FIRRTL-NEXT: connect mem.readwritePorts[2].readData, mem_sram.RW2.rdata
-  // FIRRTL-NEXT: connect mem_sram.RW2.wdata, mem.readwritePorts[2].writeData
-  // FIRRTL-NEXT: connect mem_sram.RW2.wmode, mem.readwritePorts[2].isWrite
-  // FIRRTL-NEXT: connect mem_sram.RW2.wmask, UInt<1>(1)
-  val mem = SRAM(1024, UInt(8.W), 2, 2, 3)
-
-  // FIRRTL-NEXT: connect mem.readPorts[0].address, pad(UInt<7>(100), 10)
-  // FIRRTL-NEXT: connect mem.readPorts[0].enable, UInt<1>(1)
+  // VERILOG: module mem_sram_1024x8
+  val mem = SRAM(1024, UInt(8.W), 1, 1, 1)
+
   mem.readPorts(0).address := 100.U
   mem.readPorts(0).enable := true.B
+  mem.writePorts(0).address := 5.U
+  mem.writePorts(0).enable := true.B
+  mem.writePorts(0).data := 12.U
+  mem.readwritePorts(0).address := 5.U
+  mem.readwritePorts(0).enable := true.B
+  mem.readwritePorts(0).isWrite := true.B
+  mem.readwritePorts(0).writeData := 100.U
 
-  // FIRRTL-NEXT: wire foo : UInt<8>
-  // FIRRTL-NEXT: connect foo, mem.readPorts[0].data
   val foo = WireInit(UInt(8.W), mem.readPorts(0).data)
-
-  // FIRRTL-NEXT: connect mem.writePorts[1].address, pad(UInt<3>(5), 10)
-  // FIRRTL-NEXT: connect mem.writePorts[1].enable, UInt<1>(1)
-  // FIRRTL-NEXT: connect mem.writePorts[1].data, pad(UInt<4>(12), 8)
-  mem.writePorts(1).address := 5.U
-  mem.writePorts(1).enable := true.B
-  mem.writePorts(1).data := 12.U
-
-  // FIRRTL-NEXT: connect mem.readwritePorts[2].address, pad(UInt<3>(5), 10)
-  // FIRRTL-NEXT: connect mem.readwritePorts[2].enable, UInt<1>(1)
-  // FIRRTL-NEXT: connect mem.readwritePorts[2].isWrite, UInt<1>(1)
-  // FIRRTL-NEXT: connect mem.readwritePorts[2].writeData, pad(UInt<7>(100), 8)
-  mem.readwritePorts(2).address := 5.U
-  mem.readwritePorts(2).enable := true.B
-  mem.readwritePorts(2).isWrite := true.B
-  mem.readwritePorts(2).writeData := 100.U
-
-  // FIRRTL-NEXT: connect mem.readwritePorts[2].address, pad(UInt<3>(5), 10)
-  // FIRRTL-NEXT: connect mem.readwritePorts[2].enable, UInt<1>(1)
-  // FIRRTL-NEXT: connect mem.readwritePorts[2].isWrite, UInt<1>(0)
-  mem.readwritePorts(2).address := 5.U
-  mem.readwritePorts(2).enable := true.B
-  mem.readwritePorts(2).isWrite := false.B
-
-  // FIRRTL-NEXT: wire bar : UInt<8>
-  // FIRRTL-NEXT: connect bar, mem.readwritePorts[2].readData
-  val bar = WireInit(UInt(8.W), mem.readwritePorts(2).readData)
+  val bar = WireInit(UInt(8.W), mem.readwritePorts(0).readData)
 }
 
-println(lit.utility.panamaconverter.firrtlString(new Sram))
+println(lit.utility.panamaconverter.verilogString(new Sram))
 
 // FIRRTL-LABEL: public module WireAndReg :
 // FIRRTL-NEXT:   input clock : Clock

diff --git a/lit/tests/Property/Good.sc b/lit/tests/Property/Good.sc
@@ -8,7 +8,7 @@ import chisel3.panamaom._
 import lit.utility._
 
 // SFC-FIRRTL-LABEL: circuit IntPropTest :
-// SFC-FIRRTL-NEXT: module IntPropTest :
+// SFC-FIRRTL: module IntPropTest :
 // SFC-FIRRTL-NEXT: output intProp : Integer
 class IntPropTest extends RawModule {
   val intProp = IO(Output(Property[Int]()))

diff --git a/lit/tests/SmokeTest.sc b/lit/tests/SmokeTest.sc
@@ -11,14 +11,18 @@ class FooBundle extends Bundle {
 }
 
 // SFC-FIRRTL-LABEL: circuit FooModule :
-// SFC-FIRRTL-NEXT:    module FooModule :
+// SFC-FIRRTL-NEXT:    layer Verification, bind, "Verification" :
+// SFC-FIRRTL-NEXT:      layer Assert, bind, "Verification/Assert" :
+// SFC-FIRRTL-NEXT:      layer Assume, bind, "Verification/Assume" :
+// SFC-FIRRTL-NEXT:      layer Cover, bind, "Verification/Cover" :
+// SFC-FIRRTL-NEXT:    public module FooModule :
 // SFC-FIRRTL-NEXT:      input clock : Clock
 // SFC-FIRRTL-NEXT:      input reset : UInt<1>
 // SFC-FIRRTL-NEXT:      output io : { flip foo : UInt<3>}
 // SFC-FIRRTL:           skip
 
 // MFC-FIRRTL-LABEL: circuit FooModule :
-// MFC-FIRRTL-NEXT:    module FooModule :
+// MFC-FIRRTL-NEXT:    public module FooModule :
 // MFC-FIRRTL-NEXT:      input clock : Clock
 // MFC-FIRRTL-NEXT:      input reset : UInt<1>
 // MFC-FIRRTL-NEXT:      output io : { flip foo : UInt<3> }

diff --git a/panamaconverter/src/PanamaCIRCTConverter.scala b/panamaconverter/src/PanamaCIRCTConverter.scala
@@ -75,7 +75,7 @@ object Reference {
   final case class SubIndexDynamic(index: MlirValue, tpe: fir.Type) extends Reference
 }
 
-case class WhenContext(op: Op, parent: MlirBlock, var inAlt: Boolean) {
+case class BlockContext(op: Op, parent: MlirBlock, var inAlt: Boolean) {
   def block: MlirBlock = op.region(if (!inAlt) 0 else 1).block(0)
 }
 
@@ -139,7 +139,7 @@ class InnerSymCache {
 class FirContext {
   var opCircuit: Op = null
   var opModules: Seq[(String, Op)] = Seq.empty
-  val whenStack = mutable.Stack.empty[WhenContext]
+  val blockStack = mutable.Stack.empty[BlockContext]
   val valueCache = new ValueCache
   val innerSymCache = new InnerSymCache
 
@@ -155,17 +155,17 @@ class FirContext {
     opModules = opModules :+ (name, newModule)
   }
 
-  def enterWhen(whenOp: Op): Unit = whenStack.push(WhenContext(whenOp, currentBlock, false))
-  def enterAlt():  Unit = whenStack.top.inAlt = true
-  def leaveWhen(): Unit = whenStack.pop
+  def enterBlock(op: Op): Unit = blockStack.push(BlockContext(op, currentBlock, false))
+  def enterAlt():   Unit = blockStack.top.inAlt = true
+  def leaveBlock(): Unit = blockStack.pop
 
   def circuitBlock: MlirBlock = opCircuit.region(0).block(0)
   def findModuleBlock(name: String): MlirBlock = opModules.find(_._1 == name).get._2.region(0).block(0)
   def currentModuleName:  String = opModules.last._1
   def currentModuleBlock: MlirBlock = opModules.last._2.region(0).block(0)
-  def currentBlock:       MlirBlock = if (whenStack.nonEmpty) whenStack.top.block else currentModuleBlock
-  def currentWhen:        Option[WhenContext] = Option.when(whenStack.nonEmpty)(whenStack.top)
-  def rootWhen:           Option[WhenContext] = Option.when(whenStack.nonEmpty)(whenStack.last)
+  def currentBlock:       MlirBlock = if (blockStack.nonEmpty) blockStack.top.block else currentModuleBlock
+  def currentWhen:        Option[BlockContext] = Option.when(blockStack.nonEmpty)(blockStack.top)
+  def rootWhen:           Option[BlockContext] = Option.when(blockStack.nonEmpty)(blockStack.last)
 }
 
 class PanamaCIRCTConverter(val circt: PanamaCIRCT, fos: Option[FirtoolOptions], annotationsJSON: String) {
@@ -1192,13 +1192,27 @@ class PanamaCIRCTConverter(val circt: PanamaCIRCT, fos: Option[FirtoolOptions],
       .withOperand( /* condition */ cond.value)
       .build()
 
-    firCtx.enterWhen(op)
+    firCtx.enterBlock(op)
     visitIfRegion()
     if (visitElseRegion.nonEmpty) {
       firCtx.enterAlt()
       visitElseRegion.get()
     }
-    firCtx.leaveWhen()
+    firCtx.leaveBlock()
+  }
+
+  def visitLayerBlock(layerBlock: LayerBlock, visitRegion: () => Unit): Unit = {
+    val loc = util.convert(layerBlock.sourceInfo)
+
+    val op = util
+      .OpBuilder("firrtl.layerblock", firCtx.currentBlock, loc)
+      .withNamedAttr("layerName", circt.mlirFlatSymbolRefAttrGet(layerBlock.layer.name))
+      .withRegion(Seq((Seq.empty, Seq.empty)))
+      .build()
+
+    firCtx.enterBlock(op)
+    visitRegion()
+    firCtx.leaveBlock()
   }
 
   def visitDefInstance(defInstance: DefInstance): Unit = {
@@ -1325,7 +1339,7 @@ class PanamaCIRCTConverter(val circt: PanamaCIRCT, fos: Option[FirtoolOptions],
       .withNamedAttr("name", circt.mlirStringAttrGet(Converter.getRef(firrtlMemory.id, firrtlMemory.sourceInfo).name))
       .withNamedAttr("nameKind", circt.firrtlAttrGetNameKind(FIRRTLNameKind.InterestingName))
       .withNamedAttr("annotations", circt.emptyArrayAttr)
-      .withNamedAttr("portAnnotations", circt.emptyArrayAttr)
+      .withNamedAttr("portAnnotations", circt.mlirArrayAttrGet(ports.map(_ => circt.emptyArrayAttr)))
       .withResults(ports.map { case (_, tpe) => tpe })
       .build()
     val results = ports.zip(op.results).map { case ((name, _), result) => name -> result }.toMap
@@ -1884,6 +1898,7 @@ object PanamaCIRCTConverter {
           if (when.elseRegion.nonEmpty) { Some(() => visitCommands(parent, when.elseRegion.result)) }
           else { None }
         )
+      case layerBlock:          LayerBlock                   => visitLayerBlock(layerBlock, () => visitCommands(parent, layerBlock.region.result))
       case defInstance:         DefInstance                  => visitDefInstance(defInstance)
       case defMemPort:          DefMemPort[ChiselData]       => visitDefMemPort(defMemPort)
       case defMemory:           DefMemory                    => visitDefMemory(defMemory)
@@ -1945,6 +1960,14 @@ object PanamaCIRCTConverter {
   ): Unit = {
     cvt.visitWhen(when, visitIfRegion, visitElseRegion)
   }
+  def visitLayerBlock(
+    layerBlock:  LayerBlock,
+    visitRegion: () => Unit
+  )(
+    implicit cvt: PanamaCIRCTConverter
+  ): Unit = {
+    cvt.visitLayerBlock(layerBlock, visitRegion)
+  }
   def visitDefInstance(defInstance: DefInstance)(implicit cvt: PanamaCIRCTConverter): Unit = {
     cvt.visitDefInstance(defInstance)
   }

diff --git a/tests.sc b/tests.sc
@@ -89,7 +89,7 @@ trait LitModule extends Module {
     PathRef(T.dest)
   }
   def run(args: String*) = T.command(
-    os.proc("lit", litConfig().path)
+    os.proc("lit", litConfig().path, "-a")
       .call(T.dest, stdout = os.ProcessOutput.Readlines(line => T.ctx().log.info("[lit] " + line)))
   )
 }