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[DebugInfo] Emit source language scala type information and pass it to CIRCT #4224

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@rameloni rameloni commented Jun 27, 2024

This is a first attempt for generating and propagating scala source language type information to CIRCT #4015.
This PR adds a new option to support the new backend of my project: a type-based waveform viewer. Chisel currently misses an open-source waveform viewer and tywaves is adding support for Chisel to Surfer.

I wrote more details about the internal changes here: https://github.com/rameloni/tywaves-chisel-demo/wiki/Changes-in-Chisel.
While the full wiki contains also details about the integration of the different components involved.

Specific Chisel contributions

  • Extract scala type name and constructor parameters (type, name, value)
  • Encode that information into an annotation for each circuit element and pass to CIRCT through the FIRRTL annotations (probably the intrinsics are a better solution, but to get things started I think annotations system is more than enough)
  • Integrate it in ChiselStage through the PhaseManager between the Elaborate and Convert phases
  • Add an option to ChiselStage for generating or not that information

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  • Did you add Scaladoc to every public function/method?
  • Did you add at least one test demonstrating the PR?
  • Did you delete any extraneous printlns/debugging code?
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  • Did you add appropriate documentation in docs/src?
  • Did you request a desired merge strategy?
  • Did you add text to be included in the Release Notes for this change?

Type of Improvement

  • Feature (or new API)
  • Backend code generation

Desired Merge Strategy

  • Squash: The PR will be squashed and merged (choose this if you have no preference).
  • Rebase: You will rebase the PR onto master and it will be merged with a merge commit.

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- Create `TywavesAnnotation` (firrtl) case class to represent the annotation
- Add companion object to generate `TywavesChiselAnnotation`s for Chisel circuit: it parses a chisel circuit, extracts the necessary information from each component, and annotates each FIRRTL target
- Support annotation for IO ports
- Add support for modules and data types (grounds, aggregates, and user-defined (only extended bundles))
- Support nested modules and data types
- Create `AddTywavesAnnotations` phase to add the TywavesAnnotation to the elaborated Chisel circuit
- Update `ChiselStage` to integrate `AddTywavesAnnotation` phase (run before `Convert` phase only if `withDebug` is true)
- Added following tests:
        - Module tests:
		- Empty module
		- Module with submodule(s)
		- Modules with parameters and paremetrized modules (need to extract scala meta-programming information though)
		- BlackBoxes
		- Intrinsics
		- Classes
        - Ports test:
		- Explict Clock, SyncReset (Bool), AsyncReset and Reset
		- Implicit clock and reset
		- Ground types: Bool, UInt, SInt, Analog
		- Bundles: empty, anonymous, user-defined, nested
		- Vecs: 1-D, 2-D
		- MixedVec
		- Vecs of bundles
		- Bundles of vecs
- Added "createAnno" from DefWire, DefRef, DefRegInit case
- Reorganize test structure making reusable modules for different bindings (IO, Reg, Wire)
- Added following tests:
        - Ports tests:
		- Ports inside a submodule
        - Wire/reg tests:
                - Explict Clock, SyncReset (Bool), AsyncReset and Reset
		- Implicit clock and reset
		- Ground types: Bool, UInt, SInt
		- Analog (only wires)
		- Bundles: empty, anonymous, user-defined, nested
		- Vecs: 1-D, 2-D
		- MixedVec
		- Vecs of bundles
		- Bundles of vecs
		- Wires/regs inside a submodule
- Move module and data types tests in different subdirectories
- Add readmes with output samples of the annotations
- Added "createAnno" from DefMemory, DefSeqMemory, FirrtlMemory and DefMemPort case
- Implement "createAnnoMem" to create a TyeavesAnnotation for memory (a memory does not extend the Data type)
- Return empty annotations from Connect, DefInvalid
- Add warning message for "Unhandled circuit commands"
- Added the following tests:
	- ROM of ground type
	- SyncReadMem (when UNUSED) of ground type, aggregate types (bundle)
	- Mem (when UNUSED) of ground type, aggregate types (bundle)
	- SRAM of ground type (with different combs of ports), aggregate types
	- SyncReadMem (when USED) of ground type, aggregate types (this instantiate MPORT)
        - Mem (when USED) of ground type, aggregate types (this instantiate MPORT)
…of Vecs)

- Added the following tests:
	- Masked memories (SyncReadMem, Mem, SRAM)
…onstructor (it works for any scala class)

[Fix tywaves] Fix annotation issue for first parameter of the constructor

Sometimes the first parameters was skipped. The `getConstructorParams` was dropping the first element of the list assuming that it contained the class itself and not a parameter.
This assumption worked only for some cases ("$outer" is not always present in first position). Now the method is improved by doing a filter map (collect).

Update report output samples in tests readmes

Annotate types with parameters in the scala constructor (it works for any scala class)

- Create a case class (`ClassParam`) to represent the parameters of a class in the firrtl annotation
- Update `TywavesAnnotation` with `params: Option[Seq[ClassParam]]`. Some classes may not have any parameter
- Implement `getConstructorParams()` to get params of a constructor of any scala class. It uses scala reflection.
- Added the following tests:
	- Test getConstructorParams() for:
		- classes
		- case classes
		- private, protected and public fields in the constructor: name, type and value accessible
		- fields in the body of a class (expected behaviour not accessible)
		- parameters in the constructor (no val): only name and type accessible
- Updated the following tests:
	- Vec tests of DataTypesSpec: chisel Vecs have a length parameter in the constructor
	- Mem tests: memories contain constructs with parameters in their constructors
	- Module tests: update the module with parameters test
…s type of chisel3.Data

Now it returns only the value without the complete name (packageName.type.name) of the parameter.

- Fix hasParams: sometimes some parameters of a class were not detected.
- Added the following tests:
        - Circuit with parameters (scala basic types, scala classes, and chisel types)
        - Bundles with parameters (scala basic types, scala classes, and chisel types)
- Updated tests (scala fmt and bug fix):
        - TypeAnnotationMemSpec
        - TypeAnnotationModuleSpec
        - TypeAnnotationDataTypesSpec
- Fix scalafmt errors
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The generation of annotations still misses support for some Chisel constructs like ChiselEnum, therefore the PR is not ready yet for a merge.

@rameloni rameloni marked this pull request as draft June 27, 2024 15:42
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