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Fixed-latency dual-parallel lookup table (CAM-like) mostly for AllowedIP lookups in RX/TX path

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Scalable Pipelined Lookup (FPGA)

Dual-parallel fixed-latency lookup (CAM-like) of IP address prefixes.

This uses state-of-the-art research (2022) on a novel tree structure; 30% more efficient than existing solutions.

Available in SystemVerilog and a subsequent SpinalHDL rewrite.

Re-usable in router and switch applications.

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Fixed-latency dual-parallel lookup table (CAM-like) mostly for AllowedIP lookups in RX/TX path

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  • Scala 52.8%
  • SystemVerilog 33.3%
  • C++ 7.4%
  • Verilog 5.2%
  • Makefile 1.3%