OpenOCD with STM32L082 not handling IWDG/WWDG/STOP/SLEEP correctly

[dmeehan1968]

I'm using JetBrains CLion as a development environment, with OpenOCD and GDB as the flash/debug toolchain.

I have a custom board with STM32L082CZ, similar to the B-LR072-LRWAN1 board.

I have previously been using STM32CubeIDE and its integrated flash/debug facility and this has worked ok, although I was trying to switch to CLion as I found the Cube IDE performance under macOS to be poor. I also develop for other MCU with different toolchains and was looking to standardise.

I discovered that it was desirable to use the STMicroelectronics/OpenOCD openocd-cubeide-r4 release, as opposed to the openocd-org/openocd 0.11.0 release as the STML0 family was, at least at some point, not fully supported. Specifically, STM32L0 has dual memory banks and this is not configured in the stml0discovery.cfg file provided with the official openocd release. This is provided in the STM/OpenOCD release.

The specific problem I was encountering was constant disconnects/non-communication with the device. Flashing worked ok, but debugger stability was poor to non-existent. I discovered largely through trial and error that the debugger was:

• Not disabling IWDG and WWDG timers when under debugger control, so if I held the programme at a breakpoint for too long the MCU would reset.
• Not enabling debugger in STOP and SLEEP modes correctly, resulting in each 'step' in the debugger losing track/control of the MCU and ultimately failing to debug as required.

I altered my code to disable STOP/SLEEP states and disabled use of IWDG/WWDG and found that the debug stability vastly improved.

I followed the openocd configuration files in use, including the linkages from the dual memory config to the base config, and found that both of these processes are controlled by events within the stm32l0.cfg file. I verified that the memory addresses are correct, and the bitfield values, as per the STM docs for the MCU.

So it seems that for some reason, these settings are not being correctly applied, either not triggered at the appropriate points or the writes do not succeed.

Whilst I have worked around the problem, it would be great if this was better documented (it took me several hours of searching on forums etc to find the relevant information, plus a degree of trial and error), and whatever the reason for the failure to be resolved.

--------------------------------------------------------
st-info --probe output
--------------------------------------------------------
Found 1 stlink programmers
 version:  V2J29S7
 serial:   55FF74067880565352161467
 flash:   196608 (pagesize: 128)
 sram:    20480
 chipid:   0x0447
 descr:   L0xx Category 5

--------------------------------------------------------
config for openocd
--------------------------------------------------------

source [find interface/stlink.cfg]

transport select hla_swd

set WORKAREASIZE 0x2000

# L082 has dual bank memory
source [find target/stm32l0_dual_bank.cfg]

reset_config srst_only

# required to allow device reset when unresponsive
reset_config connect_assert_srst

--------------------------------------------------------
output for openocd (with MCU code changed to remove IWDG/WWDG/STOP/SLEEP
--------------------------------------------------------
/usr/local/bin/openocd -s /usr/local/share/openocd/scripts -f /<redacted>/SD01-L-V2/src/board/SD01-L-STM32L082/openocd/stm32l082.cfg -c "tcl_port disabled" -c "gdb_port disabled" -c "tcl_port disabled" -c "program \"/<redacted>/SD01-L-V2/dist/SD01-L-V2-0-0-1-Debug.elf\"" -c reset -c shutdown
Open On-Chip Debugger 0.11.0+dev-00454-gd3b71197b-dirty (2022-09-04-13:46) [https://github.com/STMicroelectronics/OpenOCD]
Licensed under GNU GPL v2
For bug reports, read
	http://openocd.org/doc/doxygen/bugs.html
Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
srst_only separate srst_nogate srst_open_drain connect_assert_srst

Info : clock speed 300 kHz
Info : STLINK V2J29S7 (API v2) VID:PID 0483:3748
Info : Target voltage: 3.245026
Info : stm32l0.cpu: Cortex-M0+ r0p1 processor detected
Info : stm32l0.cpu: target has 4 breakpoints, 2 watchpoints
Info : gdb port disabled
Info : Unable to match requested speed 300 kHz, using 240 kHz
Info : Unable to match requested speed 300 kHz, using 240 kHz
target halted due to debug-request, current mode: Thread 
xPSR: 0xf1000000 pc: 0x08010064 msp: 0x20005000
STM32L0: Enabling HSI16
Info : Unable to match requested speed 2500 kHz, using 1800 kHz
Info : Unable to match requested speed 2500 kHz, using 1800 kHz
** Programming Started **
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (0) size is 96kb, base address is 0x8000000
Info : Device: STM32L0xx (Cat.5)
Info : STM32L flash has dual banks. Bank (1) size is 96kb, base address is 0x8018000
** Programming Finished **
Info : Unable to match requested speed 300 kHz, using 240 kHz
Info : Unable to match requested speed 300 kHz, using 240 kHz
shutdown command invoked